Invention relates generally to functional verification of integrated circuit designs, particularly to verification of very large scale integrated-circuits (VLSI) comprising complex functional blocks, including intellectual property (IP) cores.
Advances in circuit design and fabrication technologies enable designers to pack millions of transistors on single integrated circuit chips. Designs of such complexity typically require effort of team size ranging from few to hundred designers. In the design process, computer-aided design or engineering (CAD/CAE) tools are used to define and verify circuits as design process progresses. Good design practice also follows modular design style, whereby design is broken-down into smaller, more manageable functional blocks. Such sub-blocks are assigned to smaller teams of engineers, such that teams proceed in parallel to design and verify sub-blocks. Separately designed and verified functional blocks are then integrated to define whole circuit.
Logic simulation may be used to verify chip designs, both at block and chip levels. Simulators may support hardware description languages (HDL), used to formally describe chip designs. Such languages include set of basic elements. Built-in simulator instructions model stimulus and response behavior of basic element types. Verification process involves providing stimuli (i.e., pattern vectors), in cycle-by-cycle manner as external inputs to subject block or chip.
Input vectors are provided for simulation, along with HDL description of subject design. Based on modeling of behavior of basic elements used in subject design and interconnection or interaction among such basic elements, simulator determines outputs to be generated by subject design. Functional verification then serves to verify whether simulator-generated values match results that subject design is expected to produce. Typically, large sequences of input vectors are created to verify correct design functionality.
Unrelenting rise in design complexity results in modular design approach, whereby multiple design teams develop and verify functional sub-blocks, which are then integrated to create final system design. To enhance design productivity and make development of highly complex integrated circuits (i.e., so-called system-on-a-chip (SoC) integrated circuits) manageable, sub-blocks may be provided as reusable cores for other circuit designs. SoC reuse approach is appropriate where certain functional block performs well-defined, commonly-needed function, such as popular processor core, special D/A or A/D converter, standard bus interface, or such block implements special algorithms such as MPEG decode.
In this manner, so-called intellectual property (xe2x80x9cIPxe2x80x9d) cores are provided for developing reusable core modules for licensing to other companies, without necessarily building circuit products. Circuit design employing reusable cores may be referred to as core-basedxe2x80x9d design, regardless whether such cores are developed for same design, taken from previous design, or licensed from other design source.
In core-based design, individual cores may be developed and verified independently as stand-alone modules, particularly when IP core is licensed from external design. source. To verify module design, core development team creates set of test vectors to simulate and exercise subject design, performed at core interface level, and input/output (I/O) signals at such level are not observable externally from such chip.
Upon system chip integration, regardless of such cores being developed in-house or sourced externally, another set of test vectors are created, preferably based on I/O signals and chip external interface for integrated design verification. Test vectors developed for module-level verification are typically not used at chip level, and original development team understanding of proper core functioning is not necessarily provided to benefit integration verification phase, particularly when core is externally sourced. Further, design problems arising during integration often result from functional interaction between cores. Hence, misunderstanding may significantly contribute to design mistakes during such integration phase, typically being phase of increased time pressure.
Reusable or IP-core based design involves thorough block-level verification. Comprehensive input stimuli are applied to subject circuit using simulation to exercise design adequately. Stimuli application drives subject circuit through successive states, e.g., 0/1 status of storage elements in subject design. If verification is deemed complete, then states traversed by applying stimuli are considered legitimate-states, and such core is passed on for real operation. Such data represent knowledge base associated with proper functioning of subject core module. Applying such knowledge base may be useful for subsequent integration verification process.
During integration stage, IP cores are brought together, and chip-level verification commences. Stimuli needed to drive functional blocks, instead of being provided by external means, derive from outputs of other functional blocks with which subject block may interact. In similar manner, outputs of certain block, which previously needed to be verified externally, serves as input stimuli driving other interacting blocks. No immediate validation is typically provided as to whether each functional block operates properly.
As stimuli are applied during chip-level simulation, entire chip, as well as each of functional blocks, passes through successive operating states. From perspective of functional block, operating state external to set of legitimate states may indicate following conditions:
(i) True Error: Stimuli as provided by surrounding interacting blocks steer block to undesignated state. Upon such occurrence, subsequent operations of such block may not produce proper result. If such occurrence is undetected and flagged, undesired behavior of such block may propagate to other interfacing blocks, thereby leading to other error conditions. However, circuit location where problem occurs may be far from where such condition originates, i.e., in terms of space or time.
(ii) False Error: State has not occurred during module verification.
However, such condition is legitimate, and poses no problem to correct design functionality.
(iii) Un-exercised State: This refers to state that has not occurred during block level verification, but may indicate design problem. Hence, user is notified of such occurrences for further analysis of design logic.
Recent attempts provide tools to enhance quality or quantity of verification coverage or aid in operation of verification process. For example, various code coverage tools analyze simulation runs to measure percentage of HDL code traversed during simulation. While providing useful measurement of degree of verification thoroughness, code coverage technique actually focuses more on form rather than design substance.
Further, hardware verification language (xe2x80x9cHVLxe2x80x9d) is used to enable designers to specify more conveniently verification operations for subject design, thereby complementing HDLs used to specify subject design. However, HVL technique focuses on easing test vector generation task. Development or coding of verification specification is largely tedious, manual operation.
Invention resides in computer-implemented apparatus and/or method for functional verification of integrated circuit design. Preferably, present approach provides automatic generation of system or circuit design from reusable functional block or IP core using logic simulator and set of input stimuli, and rule base which captures set of states or scenarios.
Occurrence of each state allows designer to conclude either: (i) usage of module is legitimate and proper, (ii) misuse of module has occurred, or (iii) usage has taken module to state that designer has not expected. Rule base is embedded in module to create effectively intelligent core. When collection of core modules for chip design are brought together during integration phase, intelligence embedded in rule bases may aid in integration verification process.
Preferred implementation uses computer or software-based system that analyzes functional block using logic simulator and set of pattern vectors to derive set of rules (i.e., rule base) to aid in chip design verification during integration testing. Operations performed by such computer system include automatic categorization of types of logic contained in subject design, automatic recognition of finite state machines (FSM), automatic partitioning of subject design into logic clusters, and automatic generation of rule base for later use in integration verification. During integration testing, exerciser module uses rule bases embedded in functional blocks to identify potential mistakes in operations of and interactions among subject design modules.